Semiconductor design

Silicon for governed computing

Processors check whether code is allowed to run. They don't check whether an action is supposed to happen. We design hardware that does.

The family

Two designs, one idea

Illustration of the CEU
RTL · FPGA prototype

CALM Enforcement Unit (CEU)

A standalone enforcement chip. It sits beside a processor, physically separate from it, and stands between what a system decides to do and what it is allowed to do.

The CEU is the foundation of the family: every MPU carries one.

MPUsSiliconA governance-native processor in silicon, built from tiles.
MPUnNanoThe same design for a carbon-nanotube substrate.
MPUqQuantumThe same design as the controller for quantum hardware.
RTL · FPGA prototypes

Machineforce Processing Unit (MPU)

A governed processor: the rules are part of the chip, not software running on it. One design, three substrates.

Whatever it computes on, the part that checks is always classical silicon — it never runs on the hardware it is checking.

How we work

From architecture to prototype

1

Architecture

What the chip must guarantee, written down before anything is built.

2

RTL & simulation

The design in hardware description language, tested in simulation.

3

FPGA prototypes

Running on real programmable hardware. This is where the family is today.

Working with the lab

Design detail is shared under NDA. For research collaboration or government inquiries, contact the lab — Fluxive Inc. is registered on SAM.gov (UEI YCAFLE6CSKV5 · CAGE 19QJ4).